A quarterly update on Chartered Semiconductor Manufacturing’s product solutions and services

• Chartered, IBM, Infineon and Samsung Announce Design Readiness for 45nm Low-Power Technology
• Chartered Ships AMD Processors in Record Time
• Chartered 65nm Low Power Ready for Prototyping and Early Production

Design Enablement

• Chipidea Offers Advanced Mixed-Signal IP on 65nm Common Platform
• Synopsys Delivers First 65nm Reference Flow for Common Platform
• Synopsys Develops 65nm Mixed-Signal Connectivity IP for Common Platform

Value-Added Solutions

• Chartered Launches New Offering in High-Voltage Roadmap
• Chartered Launches 0.18-micron SONOS Flash for Non-Volatile Memory

2006 Chartered Multi-Project Wafer Schedule

• 65nm, 90nm, 0.13-, 0.18- and 0.35-micron

Events

• Technology Forums 2006

45nm, 65nm & 90nm

Chartered, IBM, Infineon and Samsung Announce Design Readiness for 45nm Low-Power Technology

Chartered, IBM, Infineon and Samsung have silicon-proven first functional circuits and early design kits for their jointly developed 45nm low-power process technology. The technology addresses the high-performance, low-leakage and low-power consumption needs of next-generation mobile applications. Early design kits, jointly developed by all four alliance partners, are immediately available for select customers. The 45nm low-power process is expected to be installed and fully qualified in Chartered's, IBM's and Samsung's 300mm fabs by the end of 2007. Customers can access the technology from multiple fabs, thanks to GDSII compatibility across Chartered, IBM and Samsung.

For more information, please contact your local Chartered representative or visit http://www.charteredsemi.com/media/corp/2006n/20060829.asp

Chartered Ships AMD Processors in Record Time

In June, Chartered shipped the first AMD64 processors manufactured in Fab 7. Chartered ramped 300mm production in record time and began production at mature yields. The initial AMD64 microprocessors were manufactured on 90nm process technology. AMD is scheduled to start 65nm production in Fab 7 in mid-2007.

For more information, please contact your local Chartered representative.

Chartered 65nm Low Power Ready for Prototyping and Early Production

Chartered's 65nm low-power process is on track, and we have received numerous tapeouts for test chips (with critical IPs and library components for early silicon validation) and stand-alone products. Yields demonstrated were well above expectations on the first silicon runs. We are expecting full qualification of the low-power process by early fourth quarter 2006, to be followed by the generic 65nm process by year end. Participate now in our MPW shuttle which currently supports both low-power and generic options. Submit your reservations early to avoid being left out.

For more information, please contact your local Chartered representative.

Design Enablement

Chipidea Offers Advanced Mixed-Signal IP on 65nm Common Platform

Chipidea has designed key analog and mixed-signal IP blocks on 65nm Common Platform technology. Chipidea's high-speed data converters will be available to Chartered in the third quarter of 2006. These converters are designed for SoC integration in broadband wireless communications and multimedia systems. Additionally, Chipidea's USB 2.0 High-Speed OTG physical layer (PHY), mixed-signal IP on the 65nm Common Platform technology is already taped out.

For more information, visit: http://www.chipidea.com/website/news/fullversion.do?id=580

Synopsys Delivers First 65nm Reference Flow for Common Platform

Chartered, IBM and Samsung have validated the Synopsys RTL-to-GDSII low-power reference design flow for 65nm Common Platform technology. The 65nm reference flow addresses complex design rules and directly analyzes and reduces critical areas during implementation to help companies achieve higher yields and lower chip costs.

For more information, visit: http://www.synopsys.com/news/announce/press2006/snps_cp_65nm_pr.html

Synopsys Develops 65nm Mixed-Signal Connectivity IP for Common Platform

Synopsys has developed the DesignWare® Mixed-Signal connectivity IP on 65nm for the Common Platform. These PHYs are developed to be very low power and very high performance for USB 2.0, PCI Express® (PCIe), SATA and XAUI protocols. Available today is the DesignWare USB 2.0 nanoPHY IP on Chartered and IBM's 90nm process. The 90nm IP silicon has received Hi-Speed USB logo certification.

For more information, visit: http://www.synopsys.com/news/announce/press2006/snps_ibm_charter_65nm_pr.html

Value-Added Solutions

Chartered Launches New Offering in High-Voltage Roadmap

Chartered has qualified a 1.8V/6V/16V offering for the 0.18-micron ultra-low leakage (ULL) in our technology roadmap for high-voltage solutions. Targeted at mobile applications in LCD drivers and power management devices, the offering is now ready for design. Further, to address the needs of amorphous TFT LCD driver, Chartered is qualifying a 32V offering by the end of third quarter 2006. Both offer non-volatile memory programmable fuse for analog trimming, 4um2 SRAM bit cell with leakage of less than 2pA/cell, and the low leakage of Chartered's 0.18-micron ULL. As part of our roadmap, we are also qualifying a 0.13-micron high-voltage solution (1.3V/ 6V) by first half 2007.

For more information, please contact your local Chartered representative.

Chartered Launches 0.18-micron SONOS Flash for Non-Volatile Memory

In July, Chartered qualified the 0.18-micron SONOS flash as part of our plan to introduce single poly non-volatile memories for embedding functions like fuse trim, code storage and features selection. The 0.18-micron SONOS flash uses the same architecture as the single poly OTP. With just three additional steps to the generic logic process, the 0.18-micron SONOS flash gives customers the flexibility to include non-volatile memory at the lowest cost of ownership.

2006 Chartered Multi-Project Wafer Schedule

Events

Chartered Technology Forums 2006 - Register TODAY!

Team Advantage - We Collaborate. You Win.
There are far too many design and manufacturing challenges to go it alone. Wouldn't it be easier with the strength and flexibility of a world-class team on your side? Come to the Chartered Technology Forums to learn more. We will showcase Chartered's collaborative approach to addressing your toughest design and manufacturing challenges.

Dates		Locations
September 28		Santa Clara Convention Center CA, USA
October 5		Ambassador Hsinchu Hotel Hsinchu, Taiwan
October 25		Intercontinental Pudong Shanghai, China
October 27		Swissotel Beijing, China

To register and find out more about our events, visit the Chartered Technology Forum website: http://www.charteredsemi.com/tf2006/

For more information, email: info@charteredsemi.com

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We have prepared this newsletter solely for your information and private circulation only. We have taken all reasonable care to ensure that the information contained in this newsletter is accurate at the time we distribute it and are not obliged to publicly update or revise any statements relating to future events or product solutions and services that we or our EDA partners may offer in the future.