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Cadence Low-Power Reference Flow for the Common Platform increases productivity for SOC design using the Common Power Format (CPF)
Cadence, IBM, Chartered and Samsung have collaborated developed several generations of Reference Flows for the Common Platform. These Reference Flows are based on the Cadence Encounter® digital IC design platform and are targeted to the Common Platform processes. The reference flows use a wire-centric methodology to address key 65nm and below SoC issues including low-power design, signal integrity, and design for manufacturing to provide the highest quality of silicon (QoS) - using metrics of power, performance and area.
65nm CPF-enabled Low-power reference flow
The Common Platform reference flow was developed for delivering volume production on advanced low-power designs. This reference flow takes advantage of Encounter GXL capabilities and provides new low power methodologies. The reference flowwas developed using the Si2 Common Power Format standard and validated with the IBM-Chartered-Samsung ARM Metro® low power libraries.
This reference flowimplements active power management which is critical at 65nm where dynamic and leakage power are siginificant factor impacting design succes. The reference flow is also addressing new design for manufacturing (DFM) challenges, addressing nanometer defect and yield issues with a proven suite of analysis and optimization capabilities embedded at critical implementation stages.
Cadence Encounter Reference Flow Features
The Cadence Low-Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation; all enabled by the Si2 Common Power Format (CPF).
This 65nm low-power flow uses the latest technologies to automate and optimize the implementation of advanced power saving techniques that include:
Clock gating-Shuts off the clock for registers in paths where the data is loaded only infrequently (but where the clock signal would continue to switch at every clock cycle and thereby drive capacitance load)
Multiple Vt Optimization-Uses multiple threshold voltage libraries to optimize for leakage power. Leakage power is reduced without compromising the timing performance
Voltage scaling-Partitions a chip into a multi-supply voltage (MSV) design, isolating parts of the silicon into islands that operate at different supply voltages based on their respective timing characteristics
MTCMOS power gating-dramatically reduces leakage power by shutting down entire regions or whole sub-blocks of a chip
Low power features
In addition to automating the task of implementing advanced power saving techniques, the Cadence Low-Power Solution provides capabilities that include:
Concurrent power-driven RTL synthesis-Encounter's global synthesis algorithm considers power, area and timing during the netlist generation, resulting in better quality of silicon
Multiple power domain analysis and optimization-Domain-aware synthesis, clock tree generation, placement, timing analysis/optimization, power and IR-drop analysis, and IR drop-induced timing and noise analysis are built-in, allowing efficient implementation of power domains
Signoff power analysis-Uses both static and dynamic analysis techniques to help designers not only estimate power and IR drop accurately but also optimize decoupling capacitance
Equivalence-checking capability-Ensures that advanced low-power implementation does not introduce logical errors, while functional checks validate the proper insertion of level shifters, isolation logic, power switches, and state-retention registers in the low power design
Availability
The Reference Flow is available now. Chartered customers can access the Cadence Chartered-IBM-Samsung low power CPF-enabled reference flow kit by following the instructions accessed here. This reference flow kit contains a reference design, documentation and scripts to run the reference flow.
Services and Support
Cadence Engineering Services specialists can assist your company with implementing part or all of this reference methodology into your development team's environment. Cadence also provides IP integration services supporting your specific design engagement needs.
For More Information
- More detail on the Cadence common platform CPF-enabled reference flow can be found in the Common Platform product brief.
- You can obtain more information on the Cadence Encounter Digital IC Design Platform.
- For questions related to obtaining the Cadence common platform CPF-enabled Reference Flow, please use the alias: common_platform_65LP@cadence.com.
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