90nm Low-Power, yield-aware reference flow

The 90nm LP Cadence, Chartered, and IBM common platform reference flow was developed for delivering volume production on advanced low power designs. This reference flow takes advantage of the current Cadence reference flow capabilities, and adds new proven low power methodologies enabled by Cadence EDA software and demonstrated from RTL to GDSII. The Encounter digital IC design platform is validated with the IBM-Chartered 90nm ARM Metro® low power libraries.

With power and leakage becoming important factors in 90nm designs and below, the Encounter platform’s capabilities for implementing active power management are critical for 90nm design success.

Cadence Encounter Low Power Reference Flow

The core of the Cadence low power solution is the production-proven Encounter low power design flow. It enables designers to easily optimize power at each design stage, and manage the highest level of complexity—50+ million gates—while delivering up to 60% reduction in power consumption. This 90nm low power flow uses the latest technologies to automate and optimize the implementation of advanced power saving techniques that include:

• Clock gating—Shuts off the clock for registers in paths where the data is loaded only infrequently (but where the clock signal would continue to switch at every clock cycle and thereby drive capacitance load)
• Multiple Vt Optimization—Uses multiple threshold voltage libraries to optimize for leakage power. Leakage power is reduced without compromising the timing performance
• Voltage scaling—Partitions a chip into a multi-supply voltage (MSV) design, isolating parts of the silicon into islands that operate at different supply voltages based on their respective timing characteristics
• MTCMOS power gating—Dramatically reduces leakage power by shutting down entire regions or whole sub-blocks of a chip

Low power features

In addition to automating the task of implementing advanced power saving techniques, the Encounter low power design flow provides capabilities that include:

• Concurrent power-driven RTL synthesis—Encounter’s global synthesis algorithm considers power, area and timing during the netlist generation, resulting in better quality of silicon
• Multiple power domain analysis and optimization—Domain-aware synthesis, clock tree generation, placement, timing analysis/optimization, power and IR-drop analysis, and IR drop-induced timing and noise analysis are built-in, allowing efficient implementation of power domains
• Signoff power analysis—Uses both static and dynamic analysis techniques to help designers not only estimate power and IR drop accurately but also optimize decoupling capacitance
• Equivalence-checking capability—Ensures that advanced low-power implementation does not introduce logical errors, while functional checks validate the proper insertion of level shifters, isolation logic, power switches, and state-retention registers in the low power design

Cadence common platform demonstration vehicle

The new 90nm low power reference methodology was verified by taking a 289K-instance (post route) consumer design from RTL to GDSII. The design was built using ARM Metro low power libraries. To achieve power reduction, it was implemented with two power domains running at 1.2V and 1.0V, as well as clock gating and multi-Vt optimization.

Steps to implementing this yield-aware low power methodology included:

• Multiple voltage domain aware synthesis
• Clock gating and multi-Vt optimization performed concurrently with the MSV synthesis
• Automatic insertion of level shifters and generation of a control file for implementation (level shifters were concurrently placed with the standard cells)
• Timing optimization performed flat using the multiple power domain infrastructure that understands the impact of various power domains on timing
• Low power clock tree synthesis used to lower the power in the clock tree
• Leakage optimization using multiple Vt libraries to further reduce leakage power
• Sign-off level power and SI analysis and optimization performed to ensure against timing or SI violations due to IR drop

For More Information:

Cadence's 90nm Low Power Reference Flow approved for the IBM-Chartered Common Platform can be accessed here. This reference flow kit contains a reference design, documentation and scripts to run the reference flow.