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90nm Generic Process Reference Flow
Cadence, IBM and Chartered have partnered to develop a RTL-to-GDSII Reference Flow to enable customers to accelerate the
path to volume silicon. This Reference Flow is based on the Cadence Encounter Platform and is targeted to the IBM-Chartered
90nm CMOS process. It uses a wire-centric methodology to address key 90nm SoC issues including low power design,
signal integrity and design for test to provide the highest quality of silicon (QoS).
- Uses "wires first" technology to deliver superior QoS for improved area utilization, lower power consumption, better timing and better test coverage
- Provides new-generation global synthesis technology to deliver superior QoS, enhanced capacity and faster run times
- Delivers the industry's leading-at-speed structural nanometer test solution to ensure better QoS and higher yields
- Supports run-time and capacity demands of 90nm designs using over 50 million gates
- Validated as compatible with the IBM-Chartered 90nm CMOS process
Encounter digital IC design platform
Key Benefits of the Cadence Encounter digital IC design platform
- Minimizes full chip iteration and time to wires by replacing traditional linear design flows with a completely new design strategy
- Ensures the highest QoS
- Optimizes wire creation for performance and manufacturability using a nanometer router
- Unified database with massive capacity of up to 50 million gates
- Efficient extensibility
Reference Methodology Process Overview
- Silicon Virtual Prototyping (SVP)
SVP is the cornerstone of the reference flow, enabling designers to go through the implementation steps necessary to validate their design assumptions in designs as large as 50 million gates.
- Placement & Physical Synthesis
Physical synthesis enables timing closure of blocks, including clock tree synthesis.
- Routing & SI Closure
The routing results at this step have minimal signal integrity violations and has met timing and manufacturability constraints in hundreds of tapeouts. The SI closure loop eliminates any remaining SI violations from the design.
- Chip-level Integration & Assembly
Chip-level integration and assembly are supported in the same environment using standard blocks for top-level integration.
- Chip Finishing & Signoff
This provides a well-proven solution for accurately validating the timing of nanometer designs while enabling detailed SI verification.
- Equivalence Checking
This is used throughout the flow to check functional equivalence of two versions of design, enabling errors to be quickly identified and corrected.
Availability
The Reference Flow is available now. Chartered customers can access the Chartered-IBM 90nm reference flow kit by following the instructions here. This reference flow kit contains a reference design, documentation and scripts to run the reference flow.
Additional information on the Chartered-IBM 90nm reference flow can be found in the IBM-Chartered product brief.
Services and Support
Cadence Engineering Services specialists can assist your company with implementing part or all of this reference methodology into your development team's environment. Cadence also provides IP integration services supporting your specific design engagement needs.
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