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Cadence Reference Flow Methodology
Providing leading edge Reference Flow Methodology
Cadence, IBM and Chartered have developed Reference Flows for the Common Platform. These Reference Flows are based on the Cadence Encounter Platform and are targeted to the Chartered-IBM 90nm CMOS process. The reference flows use a wire-centric methodology to address key 90nm SoC issues including low power design, signal integrity, and design for test to provide the highest quality of silicon (QoS).
Customers have the ability to look at their entire design at any point during the design cycle. This ensures that customers have the best possible Quality of Silicon (QoS). This will enhance a designer’s productivity and silicon reliability, as well as accelerating their time-to-volume. And by offering insight into power management at every stage of the reference flow, designers are able to fully address power reduction and optimization.
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