Memory IP

Embedded High Density Memory Solution (1T-SRAM)

	1T-SRAM-R	1T-SRAM-Q
High Density	2x the density of 6T-SRAM	4x the density of 6T-SRAM
High Speed	SRAM Performance	SRAM Performance
Capacitor	Planar	Folded (No Hi-K Dialectic Material Required)
Ease of Use	Simple Standard Interface	Simple Standard Interface
90nm	Preliminary Report Available	TBD
130nm

Test Chip and Silicon Report Status indicated above are for Nominal Process

1T-SRAM-R Technology Overview

High Density			50% smaller that 6T-SRAM
Low Cost			50%-70% lower cost that 6T-SRAM
Low Power Consumption			75% lower power than 6T-SRAM
High Speed			SRAM Performance
Ease of Manufacture			Standard Logic Process
Ease of Use			Simple standard interface

1T-SRAM-Q: Even Higher Densities

Quad Density

• Allows integration of up to 128 Mbits in 0.13um
• Allows integration of up to 256 Mbits in 90nm

Increased Performance

• Shorter wires => faster
• Shorter wires => lower power

Proven Quality

• Uses Transparent Error Correction
• Leverages standard logic processes

Embedded SRAMs Solutions (6T-SRAM)

Technology	Partner	Single Port  Dual Port		Compiler Range (bits)		Availability
				Single Port	Dual Port
65nm	Artisan			-	-	Nov 2005
90nm	Artisan			-	-	Now
	Virage			512-2M	256-512K	Dec 2005
0.13µm	Artisan			512~512K	256~256K	Now
	Virage			32~512K	32~512K	Now
	Synopsys			64~288K	64~144K	Now
0.18µm	Artisan			32~512K	32~512K	Now
	Virage			32~512K	32~256K	Now
	Synopsys			64~288K	64~144K	Now
0.25µm	Synopsys			128~144K	128~20K	Now
	Virage			64~512K	64~256K	Now
0.35µm	Synopsys			128~144K	128~16K	Now
	Virage			64~512K	NA	Now
Note: 1) CHRT´s own bitcell 2) Synopsys Passport Library

Libraries

Embedded Non-Volatile Memory Solution (NVRAM)

Features

• Flexibility
  • Allows re-programming in the system like EEPROM and Flash without special wafer processing requirements by using poly floating gate design.
• Reduces Overall System Cost
  • Because NVM can now be put onto the same die as logic w/o special processing.
• Reduced System Size
  • No separate discrete NVM in addition to logic function
• High voltage Supply is Required for Programming
  • Programming capability is same as commonly used in EEPROM and Flash
• Targeted to small and medium NVM density requirements
  • NOVeA bit cell trades off area for ease of manufacturing

Process Requirements

• No special processes required; uses standard CMOS logic process.

Silicon Validation Status

Technology Node	Test Chip Tapeout	Silicon Report Available
0.13um

Datasheets:

• NOVeA

Embedded Non-Volatile Memory Solution (OTP)

Features

• Fuse-enabled flexibility at minimal added process complexity
• Logic process for scalability and flexible integration
• Reduce design or silicon iterations to optimize time to market
• Demonstrated Reliability in high volume production
• Logic based OTP lowers your cost of ownership by
  • NVM integration to existing product without added complex modules
  • Assured re-use of IP and libraries
  • Leverage on the maturity of baseline process thereby
    • Minimum cycle time in fabrication
    • Eliminate added defect from complex modules

Comprehensive Logic-Based OTP Technology

Applications of OTP

Process Requirements

• No special processes required; uses standard CMOS logic process.

Silicon Validation Status

Technology Node	Test Chip Tapeout	Silicon Report Available
0.13um		2Q'07
0.18um
0.25um
0.35um

Datasheets:

• 0.35um OTP (One Time Programmable Embedded Memory)

Embedded Non Volatile Memory Solutions (EEPROM)

0.35um EEPROM Product Overview

Process	0.35um eEEPROM
Offering	Process
	Bitcell
	Synopsys Standard Cell Library
	Synopsys 3.3V I/O Library
	Synopsys SRAM/ROM Compiler
	VCX-Listed Analog IPs
Status	Available Now
Mem. Block Partner	BlueChips Technology

0.35um EEPROM Memory Block

• Chartered provides access to EEPROM memory block design service by Bluechips Technology"
• 128K bit (16K bit x 8) memory block is fully charactered
  • Business Model: Fully customized memory block design service
  • Memory Size Range: 64 bits ~ 128K bits
  • Delivery Time: Max. 4 weeks
  • Deliverables by BCT: Datasheet, Application Note
  • Design Views: Verilog, Timing, LVS, Place & Route, GDSII
  • 5V I/O Pad for Smart Card & Stand-alone EEPROM application
  • EEPROM Memory Block Design Service     Available NOW