Chartered Semiconductor Manufacturing and Aspec Forge Alliance

San Jose, CA -- November 18, 1996 -- Chartered Semiconductor Manufacturing and ASPEC Technology, Inc. have signed a three-year technical and marketing agreement to develop Design Implementation Technology (DIT) for Chartered’s 0.35-micron and 0.25-micron manufacturing processes. The agreement lays the foundation for systems and semiconductor companies to gain faster access to deep submicron technologies and processes and gain time-to-market advantage. The agreement is effective immediately.

Working together, ASPEC developed the 0.35-micron DIT and began delivering it to Chartered beta customers starting last July. The DIT includes gate array and standard cell libraries, I/Os, design kits, and memory compilers. The marketing arrangement will enable ASPEC to gain wider access to Chartered customers.

In the conventional business model, customers can experience a delay between the availability of a process and production of a customer’s products. The delay occurs because the development of DIT is often done after the process is fully characterized and qualified. The ASPEC/Chartered partnership is helping customers reduce these delays from as long as 6 months to less than six weeks by making the process technology, libraries and DIT available almost at the same time.

The agreement calls for Chartered to deliver early versions of its design rules and Spice models to ASPEC, so ASPEC can develop the DIT in parallel. ASPEC will also put Chartered in its priority process development list, so that it will be among the first 0.25-micron processes supported. ASPEC will also supply its QuickPort software to Chartered customers so they can retarget 0.35-micron designs to 0.25-micron designs in as little as four weeks.

Perry Constantine, ASPEC’s senior vice president for worldwide marketing and sales, said, "ASPEC sees Chartered as a key silicon foundry and is honored to be selected as a partner."

Ben Lee, Chartered vice president for worldwide marketing, said, "Time to market equals time to revenue for our customers. Working with ASPEC, we can offer a technology roadmap for fast access to deep submicron as the customer needs it."

ASPEC Technology, Inc. is a pioneer and leader in providing Open Design Implementation Technology (DIT) to ASIC vendors, IC companies and systems houses. DIT provides a standard, open link between design automation and silicon manufacturing. ASPEC’s Open DIT is based upon its patented High Density (HD) families of gate arrays (HDAs) and standard cell (HDC) libraries. It has been adopted by major semiconductor companies, including industry leaders such as AMD, Hyundai, National Semiconductor, Samsung, Winbond, Yamaha and others. ASPEC is a privately held company located at 830 E. Arques Avenue, Sunnyvale, CA 94086.

Chartered Semiconductor Manufacturing is an independent, dedicated foundry that provides quality manufacturing and exceptional customer service for semiconductor companies worldwide. Using a comprehensive range of leading-edge processes, CSM manufactures semiconductor products for a broad spectrum of market applications. CSM is headquartered in Singapore, with offices in the United States, Germany, and Taiwan. CSM is a member company of Singapore Technologies Semiconductors (STS). The STS companies provide design, integrated circuit wafer fabrication, assembly and test. STS is a strategic business unit of Singapore Technologies.