COMMON PLATFORM PARTNERS EXTEND COLLABORATION TO INTEGRATE DESIGN FOR MANUFACTURING 

Common Platform partners, EDA vendors to align on information and expertise sharing, focus on manufacturability to target customer-enabled DFM solutions

MILPITAS, Calif. and SINGAPORE - September 21, 2005 - IBM, Chartered Semiconductor Manufacturing and Samsung Electronics Co., Ltd. today announced a comprehensive, collaborative strategy and an initial set of solutions for their cross-fab, common design-for-manufacturability (DFM) initiative. The multi-faceted effort, which includes participation by leading electronic design automation (EDA) and DFM tool suppliers, will offer a series of rules, models and utility kits that provide new levels of predictability and control to achieve working silicon faster and yield ramp more efficiently. The DFM initiative builds on the companies' breakthrough jointly developed Common Platform for 90-nanometer (nm) and 65nm nodes and is supported by an extensive ecosystem of design enablement resources. Details of the DFM initiative will be unveiled at the annual Chartered Technology Forum 2005 in San Jose on September 22, 2005.

"This is a major expansion to an already unprecedented level of cooperation and focus on the most challenging issues the semiconductor industry faces. Our Common Platform approach has initially concentrated on enabling designers to leverage advanced processes in a copy-exact manner across multiple fabs," said Kevin Meyer, vice president of worldwide marketing and platform alliances at Chartered. "This is significant technically and economically for our industry. With the DFM initiative we have extended that focus to develop a standard platform that brings greater process control, higher model accuracy and increased manufacturing awareness. This results in greater predictability to customers, ensuring faster turnaround times, better yields, and optimal use of nanometer manufacturing capabilities."

The DFM initiative addresses manufacturability as the newest, most pressing design closure challenge faced by designers targeting processes at 90nm and below. It is targeted to provide enhanced depth and detail in its models, data, analysis capabilities and shapes manipulation, which are based on both statistical modeling of advanced manufacturing characteristics, as well as actual data derived from silicon production at the three manufacturing leaders.

"This is not the traditional DFM approach of providing designers with basic design rule information and SPICE models. This is an in-depth and information-rich approach to DFM," said Steve Longoria, vice president of IBM's Technology Group. "Thanks to the tight cooperation and information exchange among three of the world's most renowned manufacturers and a host of design and DFM tool experts, the common DFM platform introduces new levels of control and insight that will allow designers to create right-by-construction designs targeted at the most advanced processes available. It offers all the benefits of the Common Platform model we initiated with Chartered three years ago, and adds new capabilities specifically aimed at managing increasingly difficult issues such as yield and variability."

Shared methodology and an eight-pronged approach to the most challenging issues

The collaborative effort is targeting the development of a shared manufacturing-aware design methodology, which enables designers to quickly and efficiently identify possible yield detractors, target those that are most significant, and make intelligent trade-offs. It is focused on eight key components to meet the needs of designers implementing on leading-edge process technologies, drawing on multi-discipline expertise including design, device physics, process and manufacturing. These eight key components include:

• DFM design guidelines
• DFM checking decks
• Yield enhancement design flows
• Lithography/Shape simulation
• Chemical mechanical polishing (CMP) simulation
• Critical area analysis
• Statistical timing analysis and optimization
• DFM services, such as library certification and layout review

Individually, the focus areas will benefit from close cooperation with EDA and DFM suppliers to offer designers detailed views, guidelines and models that are based on manufacturing data for designing to the specific physical characteristics of highly complex manufacturing processes. Combined, they provide more comprehensive visibility into manufacturing effects so as to enable the designer to better anticipate yield ramp as a part of the design process.

The DFM initiative is built upon the foundation of the companies' common design enablement strategy, which includes a set of common reference flows and technology kits that support the use of the most popular EDA tools, libraries and IP cores. The resulting DFM solution will become an integral part of the Common Platform and is to be implemented through a combination of rules- and model-based design kits, containing critical information required by designers to better predict the impact of their decisions on manufactured designs over a variety of operating ranges and conditions.

The first phase release of the DFM initiative focuses on driving a correct-by-construction approach and analysis capabilities to gauge and give guidance on focus areas for improvement. Capabilities include: Updated and comprehensive DFM design guidelines for best layout practices

• Intelligent routing to address manufacturability
• Various DFM post-processing utilities, such as redundant via insertion
• Yield- and process-sensitive site analysis
• Critical area assessments

The above designer-enabled capabilities are augmented with a range of optional manufacturer-delivered DFM services including:

• Library/IP DFM review
• Full chip DFM review
• Lithography process checks
• Pattern density analysis

Future deliverables are being targeted to include customer-enabled lithography/shape simulation, CMP thickness modeling and its impact on improving parasitic extraction accuracy as well as driving more intelligent metal fill, support for statistical timing analysis and optimization, and lithography-aware/critical area-aware driven routing.

"We started with a goal of giving designers a comprehensive insight capability into the manufacturing process through inserting detailed information into their domain of design tools, IP use and verification," said Dr. Ho-Kyu Kang, vice president of Technology Development at Samsung. "Through cooperation with the core drivers of the EDA and DFM tool industries, the alliance is working with best-of-breed third-party tool vendors to have a compelling open solution for customers available from all three companies."

About Chartered

Chartered Semiconductor Manufacturing (Nasdaq: CHRT, SGX-ST: CHARTERED), one of the world's top dedicated semiconductor foundries, offers leading-edge technologies down to 90 nanometer (nm), enabling today's system-on-chip designs. The company further serves the needs of customers through its collaborative, joint development approach on a technology roadmap that extends to 45nm. Chartered's strategy is based on open and comprehensive design enablement solutions, manufacturing enhancement methodologies, and a commitment to flexible sourcing. In Singapore, the company operates a 300mm fabrication facility and four 200mm facilities. Information about Chartered can be found at www.charteredsemi.com.

Chartered Safe Harbor Statement under the provisions of the United States Private Securities Litigation Reform Act of 1995

This news release may contain forward-looking statements, as defined in the safe harbor provisions of the U.S. Private Securities Litigation Reform Act of 1995. These forward-looking statements reflect Chartered's current views with respect to future events and are subject to certain risks and uncertainties, which could cause actual results to differ materially from historical results or those anticipated. Among the factors that could cause actual results to differ materially are: changes in market outlook and trends; demands from our major customers, excess inventory and life cycles of specific products; competition from other foundries; unforeseen delays or interruptions in our plans for our fabrication facilities; the performance level of and the technology mix in our fabrication facilities; our progress on leading-edge products; the successful implementation of our collaborative efforts with IBM, Samsung and ourEDA and DFM tool suppliers; the timing and rate of the semiconductor market recovery; economic conditions in the United States as well as globally and the growth of fabless companies and the outsourcing strategy of integrated device manufacturers. Although we believe the expectations reflected in such forward-looking statements are based upon reasonable assumptions, we can give no assurance that our expectations will be attained. In addition to the foregoing factors, a description of certain other risks and uncertainties which could cause actual results to differ materially can be found in the section captioned "Risk Factors" in our Annual Report on Form 20-F filed with the U.S. Securities and Exchange Commission. You are cautioned not to place undue reliance on these forward-looking statements, which are based on the current view of management on future events. We undertake no obligation to publicly update or revise any forward-looking statements, whether as a result of new information, future events or otherwise.

[ top ]