Advanced Technology Nodes

• DFM kits available to support the Common Platform 45nm process


• Chartered expands technology agreements to 32nm

Design Enablement

• Mentor offers technology design kits for 65nm and 90nm process on the Common Platform


• Synopsys design solutions achieve compliance on the Common Platform


• Mentor's Calibre LFD validated on Chartered 65nm process


• New Design Kits/Silicon Results for AMS IP at 65nm, 90nm, 0.13 micron

2007 Chartered Multi-Project Wafer Schedule

• MPW shuttles for processes from 45nm to 0.35 micron

Events

• Chartered Technology Forums


• FSA IP Webinar


• Cadence Webinar


• Mentor EDA Tech Forums


• FSA Suppliers Expo & Conference


• CDNLive! 2007

Advanced Technology Nodes

DFM kits available to support the Common Platform 45nm process
Chartered, IBM and Samsung have made available DFM technology models, data files and design kits from leading EDA and DFM companies to support Common Platform technology at 45nm. This 45nm DFM offering supports a wide range of capabilities which addresses critical manufacturing-related issues from design to masking. The technology and tool support from leading EDA and DFM suppliers combined with manufacturing data and models from Chartered will enable customers to successfully manufacture their 45nm products.

Please visit http://www.charteredsemi.com/media/corp/2007n/20070604.asp for more information.

Chartered expands technology agreements to 32nm
Chartered and its Common Platform technology partners IBM and Samsung, along with joint-development alliance partners Infineon and Freescale, will jointly develop and manufacture chips using advanced processing technology. The 5-way joint development agreements will now include 32nm bulk CMOS process technologies and joint development of process design kits (PDKs) to support that technology. Building on the success of earlier joint development and manufacturing agreements at 90nm, 65nm and 45nm, the alliance partners will be able to produce high-performance, energy-efficient chips at 32nm. The partners plan to pool their combined expertise to design, develop and manufacture advanced technology through 2010.

Design Enablement

Mentor offers technology design kits for 65nm, 90nm process on the Common Platform
Mentor is offering a series of new mixed-signal technology design kits (TDKs) supporting Chartered’s 65nm and 90nm low-power process technology. The kits have been validated and are available for use with Mentor’s ICstudio^TM design platform. The new TDKs enable the entire analog mixed-signal IC design flow to be tailored for customers using Common Platform technology processes. Chartered and Mentor plan to broaden the TDK offerings to encompass 65nm and 90nm process variants and extend the development to 45nm.

For more information, please visit www.charteredsemi.com/design/tdks.asp or contact your local Chartered representative.

Synopsys design solutions achieve compliance on the Common Platform

Synopsys PCI Express Gen1 for the CH65LP process is the first 65nm PCI Express IP to achieve PCI/SIG compliance Synopsys’ DesignWare PHY and USB 2.0 have met industry compliance standards for interoperability and performance. Implemented on the 65nm Common Platform process, Synopsys’^TMDesignWare PHY for PCI Express and digital controller are the first 65nm IP to pass the PCI Express 1.1 compliance testing by the PCI-Special Interest Group (PCI-SIG). Additionally, its DesignWare USB 2.0 nanoPHY IP – implemented in the Common Platform 90nm process and manufactured in both Chartered and IBM, has earned the Hi-Speed USB "On-the-GO" (OTG) logo-certification by the USB Implementers Forum. The 65nm single-GDSII version of the USB 2.0 nanoPHY has been taped out by Chartered and its Common Platform partners IBM and Samsung and the first certification is under way.

For more information, please visit http://synopsys.mediaroom.com/index.php?s=43&item=452 or contact your local Chartered representative.

Mentor’s Calibre LFD validated on Chartered 65nm process
Mentor has validated its Calibre "Litho-Friendly Design" (LFD) in silicon on Chartered’s 65nm process technology. Calibre LFD allows a DRC clean cell-based design to be analyzed for manufacturability by simulating the effects of real-world lithographic process variations. Physical measurements on real test wafers processed with controlled dose and focus parameter variants were found to correlate closely with the LFD simulations. The experiments were run on an Infineon standard cell library manufactured in Chartered‘s Fab 7.

Please contact your local Chartered representative for more information.

New Design Kits/Silicon Results for AMS IP at 65nm, 90nm, 0.13 micron

Analog Bits:
Analog Bits 65nm low power PLL and DLL in CH65LP and high performance PLL and DLL in CH65G processes are available immediately.

For more information, please visit http://www.analogbits.com/commonplatform.htm or contact your local Chartered representative.

Cosmic Circuits:
A suite of Cosmic Circuits 0.13 micron power management IP and converters have been tested as well as converter IP in 90nm Common Platform Technology. This set of IP includes: LDO, Regulator, Charge Pump, Bandgap Reference, ADCs.

For more information, please visit http://www.cosmiccircuits.com/all_ip_cores.htm or contact your local Chartered representative.

Chipidea:
Chipidea has tested silicon and taped out key IP in technology nodes from 65nm to 0.13 micron.

Key highlights are: CH65G USB 2.0 test report, 65nm DAC LP, 65nm DAC G and 65nm ADC LP tested, 90nm AFE WLAN/WiFi, (m)WiMAX/Wibro, 90 ADC for Mobile TV (DMB/DVB/...) and 0.13 micron audio codec taped out.

Chipidea's IP for Chartered can be viewed at: http://www.chipidea.com/website//products/ip/technology.do?company=chartered

Please contact your Chartered account representative for more details.

True Circuits:
True Circuits 65nm PLLs and DLLs are now available for delivery in both CH65G and CH65LP processes. Silicon test reports are also available upon request. You can find True Circuits' entire line of Chartered timing IP from 180nm to 65nm by visiting:

http://www.chipestimate.com/chipestimate_ipsearch.php

Please contact your Chartered account representative for more details.

2007 Chartered Express - Multi-Project Wafer (MPW) Schedule

Don’t miss the Chartered Express MPW shuttle; get on board now!
Please contact your local Chartered representative to reserve your slot.

Events

SAVE THE DATES! Chartered Technology Forums 2007 -- Connect. Collaborate. Create.

FSA IP Webinar: Addressing the #1 Bottleneck to IP Fluidity in the Market

Please click here for event information and registration details
http://www.fsa.org/events/2007/0626w/overview.asp

Cadence Webinar: Addressing Low-Power Design Challenges on Common Platform’s 65nm Process Technology

Please click here for event information and registration details
http://www.cadence.com/webinars/webinars.aspx?xml=cdn_65nm_lowpower

Mentor EDA Tech Forums 2007

Please click here for event information and registration details
http://www.edatechforum.com/

FSA Suppliers Expo & Conference

CDNLive! 2007

Please click here for event information and registration details
http://www.cadence.com/cdnlive/na/registration.aspx?CMP=BAC-20070618_cdnlivesvreg