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Logic

Logic Technology Features

	0.60µm	0.50µm		0.35µm	0.25µm	0.18µm	0.13µm	90nm
Supply Voltage (V)	5.0	3.3	5.0	3.3/5.0	2.5/3.3	1.8/3.3	1.2/3.3,2.5	NDA required for details
Gate Stack	WSi_X	WSi_X	WSi_X	WSi_X/TiSi₂	TiSi₂	CoSi₂	CoSi₂
Isolation	LOCOS	LOCOS	LOCOS	LOCOS	STI	STI	STI
Planarization	Etch Back	Etch Back	Etch Back	CMP	CMP	CMP	CMP
Plugs	Al	Al	Al	W + CMP	W + CMP	W + CMP	Cu damascene
Metal Dielectric	TEOS + SOG	TEOS + SOG	TEOS + SOG	HDP USG + TEOS	HDP USG + TEOS	HDP USG + TEOS	F TEOS
Metal Interconnect	Al	Al	Al	Al	Al	Al	Cu

Logic Transistor Flavors

	0.60µm	0.50µm		0.35µm	0.25µm	0.18µm	0.13µm Nominal*	90nm
Vcc (V), Core/ I/O	5.0	3.3	5.0	3.3/5.0	2.5/3.3	1.8/3.3	1.2/3.3,2.5	NDA required for details
Lgate (phy) (µm), Core/I/O	0.60	0.50	0.50	0.35/0.50	0.24/0.36	0.35N,0.30P	Core:0.12/3.3V I/O: 0.35N,0.24
Tox (phy) (A), Core/I/O	125	80	100	65/100	52/70	30/63	20/65, 45
Vt_n/p (V), Core	0.80/0.85	0.56/0.76	0.65/0.77	0.60/0.75	0.57/0.57	0.48/0.48	0.34/0.36
Vt_n/p (V), I/O	na	na	na	0.75/0.77	0.60/0.60	0.60/0.615	0.61/0.61 0.49/0.50
Idsat_n/p (µA/µm), Core	487.5/270	394/192.5	535/280	540/250	610/290	600/260	535/236
Idsat_n/p (µA/µm), I/O	na	na	na	535/280	550/250	550/294	590/315, 630/300
Ioff_max_n/p (pA/µm),Core	10/10	30/30	30/30	30/30	100/100	500/500	1000/1000
Ioff_max_n/p (pA/µm),I/O	na	na	na	30/30	100/100	100/100	100/100

Overview of Logic Product Solution

	0.35µm	0.25µm	0.18µm	0.13µm	90nm
SPICE Models					NDA required for details
RC Extract Tech Files
LVS Runset
DRC Runset
Standard Cell Libraries
I/O Pad Libraries
SRAM Compiler
ROM Compiler
Cadence PDK

Revised: 03/17/2004