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Process Selection

Logic Processes

Technology	Geometry (µm)	Core I/O (V)	Process Type	Poly Layers	Metal Layers	Wafer Size	Availability
CMOS	0.09	1.0, 1.2/1.8, 2.5	Salicide	1	9	12"	Q403
	0.13	1.2/2.5, 3.3	Salicide	1	8	8"
		1.0/2.5, 3.3	Salicide	1	8	8"
	0.18	1.8/3.3	Salicide	1	6	8"
		1.8/5.0	Salicide	1	6	8"
	0.22	2.5/3.3	Salicide	1	5	8"
		2.5/5.0	Salicide	1	5	8"
	0.25	2.5	Salicide	1	5	8"
		2.5/3.3	Salicide	1	5	8"
		2.5/5.0	Salicide	1	5	8"
	0.3	3.3	Dualcide^*	1	4	8"
	0.35	3.3	Polycide	1	4	8"
		3.3	Salicide	1	4	8"
		3.3/5	Salicide	1	4	8"
	0.5	3.3	Polycide	1	3	8"
		5	Polycide	1	3	8"
	0.6	5	Polycide	1	3	8"
* Dualcide features a poly gate of tungsten silicide and source/drain of titanium silicide

Mixed-Signal Processes

Technology	Geometry (µm)	Core I/O (V)	Process Type	Poly Layers	Metal Layers	Wafer Size	Availability
CMOS	0.13	1.2/2.5, 3.3	Salicide	1	8	8"
		1.0/2.5, 3.3	Salicide	1	8	8"
	0.18	1.8/3.3	Salicide	1	6	8"
		1.8/5.0	Salicide	1	6	8"
	0.22	2.5/3.3	Salicide	1	5	8"
		2.5/5.0	Salicide	1	6	8"
	0.25	2.5	Salicide	2	5	8"
		2.5/3.3	Salicide	2	5	8"
		2.5/5.0	Salicide	1	5	8"
	0.35	3.3	Polycide	2	4	8"
		3.3	Salicide	2	4	8"
		3.3/5	Salicide	2	4	8"
	0.6	5	Polycide	2	3	8"
MIXED SIGNAL/ RF CMOS	0.13	1.2/2.5, 3.3	Salicide	1	8	8"
		1.0/2.5, 3.3	Salicide	1	8	8"
	0.18	1.8/3.3	Salicide	1	6	8"
	0.25	2.5/3.3	Salicide	2	5	8"
	0.35	3.3	Salicide	2	4	8"
Si BiCMOS	0.6	5*	Polycide	2	2	8"
SiGe BiCMOS	0.18	1.8/3.3	Salicide	1	6	8"
* NPN transistors have the option to be biased at either 3.3V or 5V

Embedded Memory

Revised: 03/17/2004