Wafer fab, process and packaging
From blank wafer to packaged die, explained step by step
Chartered Semi is a plain-language reference for chip design, wafer fabrication and advanced packaging, written for the people who work next to the process rather than around it.
Newest first
Latest explainers
The most recent guides published here, in the order they went up.
How Semiconductor IP Licensing Works: A Guide (October 2026)
How semiconductor IP licensing works in : hard core vs. soft core, upfront fees, per-chip royalties, field-of-use limits, audits and export compliance.
FPGA Design Flow for Beginners: A Simple Practical Guide (2026)
Learn the FPGA design flow for beginners with a practical path from HDL coding and simulation to synthesis, timing, implementation, and bitstream…
What an SoC Is and How It Differs from a CPU: Simple Guide 2026
What an SoC is and how it differs from a CPU: compare components, performance, power, flexibility, and uses in plain language for…
NRE Costs in Semiconductor Projects Explained: October 2026 Guide
NRE costs in semiconductor projects explained for , with realistic US estimate bands, the cost drivers that matter, and practical ways to…
What a Multi Project Wafer Shuttle Is (2026): A Practical Guide
Learn what a multi-project wafer shuttle is, how designs are grouped, what participants receive, and how engineers use the fabricated results.
How Long It Takes to Make a Chip from Design to Silicon (2026)
How long it takes to make a chip from design to silicon depends on node, verification and respins. See stage-by-stage semiconductor timelines…
What Tapeout Means in Chip Design: A Complete Guide (2026)
What tapeout means in chip design: the foundry handoff, the files you submit, signoff gates, cost drivers, schedule, and what happens to…
Power Grid Design in Chips Explained: A Beginner’s Guide 2026
Learn power grid design in chips explained in , from power delivery and IR drop to voltage droop, electromigration, decoupling and practical…
Clock Tree Synthesis Explained: A Practical Guide 2026
Clock tree synthesis explained for : how clock roots, buffers, skew balancing, CTS stages and STA reports work, and how to fix…
The process stack
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Every guide is filed under the part of the flow it belongs to, from design through fab to assembly and test.
Asked at the design review
Questions this site answers
- What actually happens during a single lithography step?
- Why can a design that passes timing still fail in silicon?
- When does advanced packaging beat moving to a smaller node?
- Which process choices drive the cost of a wafer the most?
What this site is for
A reference for how chips get made
Chartered Semi explains how a chip goes from design intent and mask data through lithography, etch and deposition to assembly, packaging and test, one step at a time and without the marketing layer.
It is written for fabless engineers, EDA and IP users, students reading their way into the industry, and anyone who needs the process described in terms they can use.