Foundry market share explained in one line: it is the slice of global semiconductor wafer fabrication revenue that a contract manufacturer captures in a given period. Here, foundry means semiconductor wafer fabrication, not metal casting or industrial foundry robotics, which is where most of the confusion on this topic comes from. Data below is as of Q2 2026.
The problem for most readers is not that the numbers are unavailable. It is that six different numbers are floating around the same quarter, and each one is measuring something slightly different. Reconciling those figures is the whole game.
Table of Contents
- What Is Foundry Market Share?
- How Is Foundry Market Share Calculated?
- How is semiconductor foundry market share calculated?
- Who Leads the Foundry Market?
- What Market Share Does Not Tell You
- Why Does Foundry Market Share Change?
- How Is the Market Split by Segment?
- How is the semiconductor foundry market split by segment?
- How Should Engineers Interpret the Rankings?
- Frequently Asked Questions
- What does foundry market share measure?
- Which company has the largest foundry market share?
- What is the difference between a pure-play foundry and an IDM?
- Is foundry market share based on revenue or wafer capacity?
- Why does foundry market share change between quarters?
- What should an engineer consider besides foundry market share?
- Conclusion: What to Check First
What Is Foundry Market Share?
Foundry market share is the percentage of total global semiconductor wafer fabrication revenue accounted for by a contract manufacturer in a given quarter. Analysts at firms such as Counterpoint Research and TrendForce sum the wafer fabrication revenue each company reports, divide by the industry total, and rank the result. That is the figure most news coverage quotes when it says a company holds roughly 73 percent of the market.
Two things are folded into that sentence that deserve separating. The first is scope: only companies that fabricate wafers for other companies count, so an integrated device manufacturer selling its own chips is either excluded entirely or included only for the wafers it makes for customers. The second is metric: revenue is the usual basis, but wafer capacity and utilization rate are also used, and they do not produce the same ranking.
Here, foundry means semiconductor wafer fabrication. If you landed on this page looking for foundry and forging robot market sizing, you are in the wrong place, and that is not a rare accident. The word collides badly on search engines.
How Is Foundry Market Share Calculated?
The core calculation is one line of arithmetic, and everything that follows is a debate about the denominator.
The numerator is the wafer fabrication revenue a company reports for the period. The denominator is the total wafer fabrication revenue across every company the analyst counts. Share is the numerator divided by the denominator, multiplied by 100. Counterpoint puts TSMC at roughly 73 percent of pure-play foundry revenue in Q2 2026. TrendForce puts it at 72.5 percent for the same quarter. The two land within half a point of each other, which is about as close as two independent research houses get.
The reconciliation problem starts when the denominator changes. A narrow pure-play denominator counts only wafer foundries. A broad Foundry 2.0 denominator adds outsourced semiconductor assembly and test providers, integrated device manufacturers with open capacity, and photomask suppliers. The same quarter that yields 72.5 percent on the narrow basis produced a figure of about 39 percent for TSMC on the broad one. Both numbers are arithmetically correct; they answer different questions.
How is semiconductor foundry market share calculated?
Analysts use reported foundry revenue rather than total company revenue, which matters more than it sounds. Samsung reports a semiconductor division that also includes memory sales, so its foundry business must be separated out before it enters the tally. Intel is the harder case: a large share of its foundry revenue is billed internally to divisions making its own processors, and analysts treat those transfers differently from external customer wafer sales. Without a consistent internal-pricing convention, two reports can disagree while both following the stated method.
Other limits are worth knowing about. Fiscal calendars rarely line up, so a December-quarter company and a December-calendar company are compared over mismatched windows. Product mix shifts what a dollar of revenue buys, since a 3nm wafer and a 65nm wafer are not the same unit of capacity. And accounting choices around depreciation of new fabs can move reported gross margin without changing how many wafers actually shipped.
| Measurement method | What it divides by | Best used for | Main weakness |
|---|---|---|---|
| Pure-play foundry revenue share | Revenue from all contract wafer manufacturers | Comparing foundries against each other | Excludes foundry services sold by IDMs |
| Foundry 2.0 value-chain share | Foundries plus OSAT, open-capacity IDMs and photomask suppliers | Mapping the whole semiconductor supply chain | Blends very different businesses into one percentage |
| Capacity share | Installed or announced wafer starts per month | Forecasting supply and pricing pressure | Capacity is not revenue; nodes differ wildly in price per wafer |
| Utilization rate | Actual wafer starts against installed capacity | Judging near-term pricing power | Company-reported, so definitions vary widely |
| Node-level share | Revenue at a specific process node band | Understanding advanced node leadership | Node definitions are not standardized across houses |
Who Leads the Foundry Market?
One company has led the semiconductor foundry market share rankings for years, and the gap has been widening rather than narrowing. TSMC held roughly 72.5 to 73 percent of pure-play foundry revenue in Q2 2026 depending on which research house you read. Samsung Foundry sits far behind at around 5.9 percent, and SMIC at roughly 5.4 percent, with UMC and GlobalFoundries both under 6 percent.
Here is the current picture with the reporting basis attached to every figure, because the basis is the point.
| Company | Q2 2026 share | Scope | Period basis | Caveat |
|---|---|---|---|---|
| TSMC | 72.5% to 73% | Pure-play foundry revenue | Calendar Q2 2026 | Includes captive demand from Apple and Nvidia silicon, which shapes the share more than most readers expect |
| Samsung Foundry | Around 5.9% | Pure-play foundry revenue | Calendar Q2 2026 | Excludes internal memory capacity from the denominator basis |
| SMIC | Around 5.4% | Pure-play foundry revenue | Calendar Q2 2026 | Concentrated in mature and mid nodes rather than the leading edge |
| UMC | Under 6% | Pure-play foundry revenue | Calendar Q2 2026 | Mature and specialty node specialist |
| GlobalFoundries | Under 6% | Pure-play foundry revenue | Calendar Q2 2026 | Holds deliberately at mature and specialty nodes |
| Top ten combined | Record quarterly revenue of USD 53.49 billion | Pure-play foundry revenue | Calendar Q2 2026 | Aggregate figure for the ten largest, not a single company share |
TSMC reported full-year 2025 foundry revenue of USD 122.54 billion, up 36.1 percent year over year, which translated to a calendar-year share near 69.9 percent. Roughly 74 percent of its wafer revenue came from 7nm-and-below advanced nodes.
The five largest foundries, ranked: TSMC at roughly 73 percent, Samsung Foundry near 6 percent, SMIC near 5.4 percent, then UMC and GlobalFoundries in the high single digits of the remaining pool. The list has barely changed in composition for a decade. What has changed is the size of the hole between first and second.
TSMC’s share has climbed steadily from about 67.6 percent in Q1 2025 to 72.5 percent in Q2 2026, with a 69.9 percent full-year 2025 average between them. That trend line matters more than any single quarter’s number, because each quarterly print is noisy and the slope is not.
| Period | TSMC share | Source basis |
|---|---|---|
| Q1 2025 | About 67.6% | Pure-play foundry revenue |
| FY2025 | About 69.9% | Calendar-year foundry revenue, USD 122.54 billion total |
| Q2 2026 | 72.5% to 73% | Pure-play foundry revenue |
| Q3 2025, broad basis | About 39% | Foundry 2.0 value chain, USD 84.8 billion market |
What Market Share Does Not Tell You
A large share is a fact about scale, not about fit. TSMC can be the obvious right answer for a 2nm AI accelerator and the wrong answer for a low-cost automotive microcontroller, and market share numbers will not tell you which case you are in.
Node availability is the first filter. If your design needs a specific process and the foundry is not running it in volume, the share number is irrelevant. Yield is second, and it is not public data for most processes. A foundry that ships at mature volume production typically has a better defect density record than one in early ramp, which matters enormously for a design with tight area budgets.
Design enablement is the filter engineers notice last but care about most. The quality of the process design kit, the standard cell libraries, the reference flows, the place-and-route support and the analog mixed-signal modelling all determine how many engineering months your tape-out costs. Two foundries offering similar nominal node names can be wildly different in this dimension.
Then there is price per good die, which is not the wafer price. Yield, mask count, die size and packaging all move the final cost. Add cycle time, capacity assurance for your volume years, fab location and the tax or subsidy regime attached to it, and access to advanced packaging such as chip-on-wafer-on-substrate capacity, which has been the binding constraint on AI accelerator output more than front-end wafers have.
Customer mix is the last one. A foundry is more reliable as a partner when its other customers are not competing directly with you in the same end market. That is a real consideration when a single customer accounts for a meaningful share of a foundry’s revenue.
Why Does Foundry Market Share Change?
Rankings move because the underlying economics move. The main forces are not mysterious, but they act on different timelines, which is why a single quarter can be misleading.
Leading-edge investment is the big one. TSMC raised its 2026 capital expenditure to a range of USD 60 to 64 billion and is running roughly 20 fabs through construction and equipment installation at once, against a historical norm of four or five. A lead measured in simultaneous fab projects is a lead measured in cash, and cash is the entry ticket nobody else in the industry currently holds.
Advanced packaging is the second lever. CoWoS capacity, not leading-edge wafer capacity, has been the practical ceiling on how many AI accelerators can ship. Whoever controls that packaging step controls more of the delivery date than wafer starts alone would suggest.
Demand mix is the third. AI accelerators and AI ASICs carry far higher average selling prices per wafer than the smartphones and PCs that dominated the earlier mix, so a shift toward AI lifts the revenue share of whoever can build those parts regardless of unit volume. Concentration on the customer side, with Nvidia, Apple, AMD and Broadcom driving large design-win pipelines, is a large part of why one company’s share moves when a single product cycle turns.
| Driver | Mechanism | Typical effect on rankings | Time to show up |
|---|---|---|---|
| Leading-edge capital expenditure | New fabs and tool sets bring node capacity online ahead of competitors | Widens the gap at the leading edge, concentrates advanced node share | Two to four years from announcement to volume |
| Advanced packaging capacity | CoWoS and similar steps cap how many advanced chips can ship | Rewards whoever has secured packaging allocation | One to two years |
| AI demand mix | Higher average selling price per wafer lifts revenue share | Raises the leader’s share even without unit growth | One to four quarters |
| Mature node overcapacity | Chinese capacity additions pressure utilization and pricing at 28nm and above | Cuts revenue and share for mature-node specialists | One to three years |
| Utilization rate | Low loading forces price concessions | Reduces reported revenue without any share of demand shifting | One quarter |
| Product cycles | A single large customer ramp or slip moves volumes between foundries | Swings quarterly share a full point or more | One to two quarters |
| Acquisitions and partnerships | Capacity or customers move between reporting entities | Reclassifies share without changing real output | Immediate on close |
| Export controls | Restrict access to tools or to customer designs in specific regions | Caps the addressable share for affected suppliers | Immediate, then compounding |
| Currency and fiscal calendars | Translation and period mismatches move reported revenue | Shifts share by tenths of a point with no operational change | One quarter |
Export controls deserve a specific mention because they work differently from everything else on this list. They do not shift share through market forces. They remove the ability to serve a customer or use a tool, and the effect on reported share arrives with a lag once the affected design cycles turn.
How Is the Market Split by Segment?
No single ranking describes the semiconductor foundry market, because the segments have opposite economics. Leading-edge logic and mature-node analog are not competing businesses; they barely compete for customers, equipment or capital.
How is the semiconductor foundry market split by segment?
Leading-edge foundry work at 3nm, 2nm and 5nm is a capital-intensive, concentrated business with a handful of credible suppliers. Mature node work at 28nm and above is a crowded, capacity-heavy business with dozens of suppliers and the opposite pricing dynamic. Specialty processes, which means RF, analog, mixed-signal, power management and non-volatile memory, reward longevity and process know-how rather than transistor density. Memory is largely captive and stays inside IDMs. Advanced packaging and OSAT services sit downstream of the wafer fab and increasingly decide the delivered product.
| Segment | Typical players | Competitive character | What drives share here |
|---|---|---|---|
| Leading-edge logic (2nm, 3nm, 5nm) | TSMC, Samsung Foundry, Intel Foundry, SMIC at selected nodes | Concentrated, capital-limited | Process lead, yield, packaging access |
| Mature node logic (28nm and above) | UMC, GlobalFoundries, SMIC, Hua Hong, Nexchip, Tower | Crowded, price-competitive | Capacity utilization and cost per wafer |
| Specialty process (RF, analog, power, embedded non-volatile memory) | GlobalFoundries, UMC, Tower, Texas Instruments, Infineon, Hua Hong | Sticky, qualification-driven | Qualification cycles and process longevity |
| Memory | Largely captive at Samsung, SK hynix, Kioxia, Micron | Not meaningfully addressable by pure-play foundries | Bit demand cycles, not foundry allocation |
| Advanced packaging | TSMC CoWoS, ASE, Amkor, Samsung | Constrained, increasingly decisive | Installed tooling and substrate supply |
| OSAT and test | ASE, Amkor, JCET, Tongfu | Scale-driven, lower margin | Test coverage, turnaround time, geography |
China’s position is worth separating from this table. SMIC, Hua Hong and Nexchip hold real global share, concentrated almost entirely in mature and mid nodes. That is where export controls bite least and where domestic overcapacity is now most acute, which is why mature-node pricing has softened while leading-edge pricing has not.
How Should Engineers Interpret the Rankings?
Use share as a screening step, then replace it with the things that actually decide whether your chip ships on time and at the right cost.
Process technology fit comes first: does the foundry run your node in volume, and how mature is that volume? Then look at design enablement, because PDK quality, IP availability, memory compilers and reference flows determine engineering cost more than the node name does. Yield learning is the third filter; a foundry that has shipped billions of good dies at your node band will beat a marginally more advanced one shipping its first.
After that come the commercial terms. Capacity assurance matters when your design enters volume, so ask about committed allocation rather than advertised wafer capacity. Then packaging and test, which for anything AI or high-bandwidth is no longer a downstream detail. Wafer price per good die, not per wafer, is the number your margin model needs.
Finally, supply-chain resilience. Concentration above roughly 70 percent in one supplier for leading-edge silicon is a structural risk, and the usual mitigation is a qualified second source at a different node rather than a hoped-for second foundry at the same one. That decision needs the market context this article provides, and then the process data that only you can evaluate.
Frequently Asked Questions
What does foundry market share measure?
It measures the percentage of global semiconductor wafer fabrication revenue held by a contract manufacturer in a given period. Analysts such as Counterpoint Research and TrendForce total the wafer revenue reported across all players they count, then divide each company’s figure by that total. The result depends heavily on scope: a pure-play basis counting only wafer foundries, or a broad Foundry 2.0 basis that adds OSAT firms, open-capacity IDMs and photomask suppliers.
Which company has the largest foundry market share?
TSMC, by a wide margin. Counterpoint Research put it at roughly 73 percent of pure-play foundry revenue in Q2 2026, with TrendForce landing at 72.5 percent for the same quarter. Samsung Foundry was second at around 5.9 percent and SMIC third at about 5.4 percent. TSMC’s full-year 2025 foundry revenue was USD 122.54 billion, up 36.1 percent year over year.
What is the difference between a pure-play foundry and an IDM?
A pure-play foundry fabricates wafers exclusively for other companies’ designs, so its customers are fabless chip designers such as Nvidia, Apple, AMD and Broadcom. An integrated device manufacturer, or IDM, designs and sells its own chips and manufactures them in its own fabs. Some IDMs, including Intel, Texas Instruments and Infineon, also sell foundry capacity externally, which creates the accounting ambiguity behind most conflicting share figures.
Is foundry market share based on revenue or wafer capacity?
Nearly always revenue. Capacity-based share, which divides installed or announced wafer starts, is used for supply forecasting but produces a very different ranking, because a 3nm wafer carries far more revenue than a 65nm wafer and requires far more tools to produce. Utilization rate is a third variant, and it is company-reported with definitions that differ between firms.
Why does foundry market share change between quarters?
Quarterly movement comes from a short list of causes: product cycles at a handful of very large customers, shifts in average selling price as AI mix changes, utilization rate swings, currency translation, and companies whose fiscal calendars do not align with the calendar year. TSMC moved from about 67.6 percent in Q1 2025 to 72.5 percent in Q2 2026, but individual quarters routinely swing a full point on ramp timing alone.
What should an engineer consider besides foundry market share?
Node availability and volume maturity, process design kit and IP quality, defect density and yield learning, wafer price per good die rather than per wafer, capacity allocation for your volume years, access to advanced packaging such as CoWoS, cycle time, and fab geography. Market share tells you who is large. It does not tell you who can build your specific part at the volume and cost you need.
Conclusion: What to Check First
Before you use any published foundry market share explained chart in a sourcing decision, pin down four things: the reporting period, the metric, the scope, and the segment your part actually sits in. A share number without those four attached is a headline, not a data point.
Then judge the foundry on process fit, design enablement, yield, capacity and packaging rather than on size alone. The market is concentrated, and that concentration is the single most important fact in it. What it does not tell you is which partner fits the chip you are actually building.
